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TranslateTang Nano 9K
Edit on 2022.05.13
Introduction
Tang nano 9K is a development board based on Gowin GW1NR-9 FPGA chip.It equips with HDMI connector, RGB screen interface connector, SPI screen connector, 32Mbit SPI flash and 6 LEDs, so users can use it for FPGA verification, risc-v soft core verification and basic function verification easily and quickly. Its 8640 LUT4 logic units can not only be used for various complex logic circuits designing, but also used for running a complete PicoRV soft core. It also meets various needs of users, such as learning FPGA, verifying soft core and further design.
Comparison
Tang Nano 9K is the 5th product of Sipeed Tang series. Before purchasing, you can compare and choose from the following table according to your demands:
| Model | Tang Nano 1K | Tang Nano 4K | Tang Nano 9K |
|---|---|---|---|
| Appearance |  |
 |
 |
| Logic Units (LUT4) | 1152 | 4608 | 8640 |
| Hard core processor | / | Cortex m3 | / |
| Crystal oscillator | 27MHZ | 27MHZ | 27MHZ |
| Display interface | RGB screen interface | HDMI | HDMI, RGB screen interface, SPI screen interface |
| Camera | / | Support OV2640 | / |
| External SPI FLASH | Reserved pads only | 32Mbits SPI flash | 32Mbits SPI flash |
| TF card slot | / | / | Yes |
| Debugger | Onboard USB-JTAG | Onboard USB-JTAG | Onboard USB-JTAG & USB-UART |
Characteristic
This form shows detail specs of Tang Nano 9K
| Item | value |
|---|---|
| Logic units(LUT4) | 8640 |
| Registers(FF) | 6480 |
| ShadowSRAM SSRAM(bits) | 17280 |
| Block SRAM BSRAM(bits) | 468K |
| Number of B-SRAM | 26 |
| User flash(bits) | 608K |
| SDR SDRAM(bits) | 64M |
| 18 x 18 Multiplier | 20 |
| SPI FLASH | 32M-bit |
| Number of PLL | 2 |
| Display interface | HDMI interface, SPI screen interface and RGB screen interface |
| Debugger | Onboard BL702 chip provides USB-JTAG and USB-UART functions for GW1NR-9 |
| IO | • support 4mA、8mA、16mA、24mA other driving capabilities • Provides independent Bus Keeper, pull-up/pull-down resistors, and Open Drain output options for each I/O |
| Connector | TF card slot, 2x24P 2.54mm Header pads |
| Button | 2 programmable buttons for users |
| LED | Onboard 6 programmable LEDs |
On-board Function block
Pinmap
| Usage | FPGA | MCU | FPGA+MCU |
|---|---|---|---|
| Language | Verilog HDL/Verilog | C/C++ | Verilog HDL/Verilog ， C/C++ |
| Introduction | verify HDL design | After flashing the softcore bitstream, this board can be used as a normal microcontroller unit |
After flashing the softcore bitstream, it can be used as two chips |
| User | Beginner，FPGA developer | RISC-V developers，Cortex-M developers | Senior engineer |
User guide
Download our packaged user guide document : Click me (All PDFs mentioned below are here)
Install IDE and configure license : Click me
Read this file (in the file downloaded in step 1) : SUG100-2.6E_Gowin Software User Guide.pdf
Read this tutorial (LEDs lighting experiment).
We suggest you recreate a project ang light the led by yourself, this can help you know more about the steps about fpga.
We recommended you read the following tips during this process:- Verilog code specifications (please search by yourself. It is very necessary to obey good code specifications from beginning)
The following documents are very useful for learning FPGA, so we should read them.
- SUG949-1.1E_Gowin HDL Coding User Guide.pdf
- UG286-1.9.1E_Gowin Clock User Guide.pdf
The documents mentioned above can be downloaded from our Download station
And there has been a compressed package contains all documentsOnline tutorial:
We suggest two excellent learning sites about verilog : HDLBITs and Verilog PageRead this tutorial (5-inch RGB screen Display tutorial). If you can't complete this experiment, you can download our 9K examples (adapted to 9K + 5-inch screen) to see which step goes wrong.
Note: for screen wiring, pay attention to the 1-pin silk screen next to the connector corresponding to 1-pin of the cable
Documents to read:- rPLL IP core reference: Click the menubar Tools>IP Core Generator>Hard Module>CLOCK>rPLL
Click to see reference
- SUG284-2.1E_Gowin IP Core Generator User Guide.pdf (Page 28)
- Datasheet of 5inch screen
- rPLL IP core reference: Click the menubar Tools>IP Core Generator>Hard Module>CLOCK>rPLL
Explanation of HDMI display (to be updated)
PicoRV soft core test (Source code)
Reference examples summary
Visit examples
Hardware files
Attention
If you have trouble with this board, you can join our telegram (t.me/sipeed) or contact us on twitter (https://twitter.com/SipeedIO). Leaving message below is also OK.
Visit Tang questions first if you have any trouble.
DO NOT USE JTAG, MODE0/1 and DONE pins. If you really need to use these pins, please refer to SUG100-2.6E_Gowin Software User Guide.pdf.
Please avoid static electricity hitting PCBA; Please release the static electricity from the hand before contacting PCBA.
The working voltage of each GPIO has been marked in the schematic . Please do not let the actual working voltage of GPIO exceed the rated value, because it will cause permanent damage to PCBA.
When connecting FPC flexible cable, make sure the cable is completely inserted into the base with on offset.
Avoid any liquid or metal touching the pads of components on PCBA during working, because this will cause short circuit and damage PCBA.
Pay attention to the multiplexed IO. The HDMI io ports are pulled up, when using these ios which are routed to pin headers, then may not meets your command.
