Edit on 2022.04.18

From this essay we can learn the basic usage of Gowin IDE

## Create project

Create Project：File-->NEW-->FPGA Dsign Project-->OK

Set project name and project path (File name and project path shoule be English)

Choose correct device:

## Prepare codes

After creating project, we can start editing codes.
To creat a new file, we can click where the arrow points to in the picture or use shortcut key Ctrl+N.
Then choose Verilog File in the pop-up window.

Name for file (Suggested using English)

Double click the created file, then edit in right window

• We use light led as an example, copy the following "LED example codes" into the created file or edit the created file by yourself.

### Verilog description

Here I just introduction some basic grammer which we will use in our code about verilog, for more knowledge please refer to the official verilog grammer.

The basic Verilog design unit is module, a module is build from 2 parts, one part describes the ports, another part describes the logic functions which show the relations between ports.

Module is like a black box we normally said, we don't care what's inside the module, we only need to instantiate the module according to the input and output format defined by the module, provide input to the module, and let the module work on its own.

A module is normally like following:

module module_name
#(parameter)
(port) ;
Function description;
endmodule


The module start with module and ends with endmodule. After declaring module we will declare the module name, then we can set parameter to make our module change automaticly to meet out depmands. Then Port is the singal dealing with this module.Function description is a kind of description how we will realize our depmands.

There are 2 signal types in a module, wire type and reg type.

Function description contains always and assign 2 functions. assign function is used for describing combinatorial logic. alyays function can be used for describing combinatorial logic, as well as timing logic.

### Example codes

module led (
input sys_clk,
input sys_rst_n,
output reg [2:0] led // 110 B, 101 R, 011 G
);

reg [23:0] counter;

always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
counter <= 24'd0;
else if (counter < 24'd1199_9999)       // 0.5s delay
counter <= counter + 1'b1;
else
counter <= 24'd0;
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
led <= 3'b110;
else if (counter == 24'd1199_9999)       // 0.5s delay
led[2:0] <= {led[1:0],led[2]};
else
led <= led;
end

endmodule


## Synthesize, constrain, place&route

### Synthesize

After finishing steps above, go to the "Process" interface, synthesize the edited file, which means running "Synthesize".

If the result is the same as shown below

It means that there is no bug in our code, we can continue the next steps.

If there is some thing wrong, please fix by yourself.

### Constrain

• Clock constraint is not involved here

To realize function of the code on FPGA, we must bind the ports we define with the chip pins.

Double click the FloorPlanner in the Process interface to set pin constrain(This can be continued if failing Synthesize).

First time open FloorPlanner it will prompt lack of ".cst" file, we just choose ok.

The led schematic of nano is as shown below:

In this GUI interface we have two ways to constrain pins:

• Drag the corresponding port to the pin of chip
• Type the pin number corresponding to the port in IO constraint(This is shown as below)

So we can do the ordered operations in the opened window as what the following picture shows:(Just choose one way)

### Place&Route

After finishing Running "Place&Route" in the Process interface window, the result will be as same as below

## Program

Double click Program Device in Process interface to open programmer application